Sparsity and power efficiency in on-die NPUs
How exploiting sparsity in neural workloads can cut power consumption in on-die NPUs, and the architecture trade-offs that come with it for low-power edge silicon.
Coming soonDownload →
Engineering articles, white papers, peer-reviewed publications and patents from the Ivarix team. The technical record behind what we build.
DSRC vs C-V2X, the brutal 100 ms latency budget, and why connected-vehicle messaging is really a hardware-acceleration problem.
Thread is the road, Matter is the language. The border router nobody mentions, and why building a Matter device is a firmware-and-silicon problem.
What an open ISA actually means, why companies are adopting it, the honest trade-offs, and why it's central to how we teach silicon design.
How exploiting sparsity in neural workloads can cut power consumption in on-die NPUs, and the architecture trade-offs that come with it for low-power edge silicon.
Our thesis on why role-based, project-driven training produces industry-ready silicon and embedded engineers faster than traditional coursework.
Abstract or one-line summary of the published research. Replace this card when your first paper is accepted.
Short description of the invention. Use the status tag to show whether it's filed, published or granted.
Occasional notes on what we're building, silicon, embedded systems, and the skill centre. No noise.